Bidirectional common-path for 8-to-24 gHz low noise SiGe BiCMOS T/R module core-chip

This thesis is based on the design of an 8-to-24 GHz low noise SiGe BiCMOS Transmitter/Receiver (T/R) Module core-chip in a small area by bidirectional common-path. The next-generation phased array systems require multi-functionality and multi-band operation to form multi-purpose integrated circuits. Wide bandwidth becomes a requirement for the system in various applications, such as electronic warfare, due to leading cheaper and lighter system solutions. Although III-V technologies can satisfy the high-frequency specifications, they are expensive and have a large area. The silicon-based technologies promise high integration capability with low cost, but they sacrifice from the performance to result in desired bandwidth. The presented dissertation targets system and circuit level solutions on the described content. The wideband core-chip utilized a bidirectional common path to surpass the bandwidth limitations. The bidirectionality enhances the bandwidth, noise, gain and area of the transceiver by the removal of the repetitive blocks in the unidirectional common chain. This approach allows succeeding desired bandwidth and compactness without sacrificing from the other high-frequency parameters. The realized core-chip has 31.5 and 32 dB midband gain for the receiver and transmitter respectively, with a + 2.1 dB /GHz of positive slope. Its RMS phase and amplitude errors are lower than 5.60 and 0.8 dB, respectively for 4-bit of resolution. The receiver noise figure is lower than 5 dB for the defined bandwidth while dissipating 112 mW of power in a 5.5 mm2 area. The presented results verify the advantage of the favored architecture and might replace the III-V based counterparts

High dynamic range low noise amplifier and wideband hybrid phase shifter for SiGe BiCMOS phased array T/R modules

Transmit/Receive Module (T/R Module) is one of the most essential blocks for Phased Array Radio Detection and Ranging (RADAR) system; due to being very influential on system level performance. To achieve high performance specifications, T/R Module structures are constructed with using III-V devices, which has some significant disadvantages; they are costly, and also consume too much area and power. As a result, application area of T/R Module is mainly restricted with the military and dedicated applications. In recent years, SiGe BiCMOS technology has started to be an emerging competitor to III-V devices, with the help of bandgap engineering. SiGe BiCMOS based T/R Module structures are facilitating similar or better performance parameters with a much lower cost, which gives a chance to T/R Module not only used for military purposes, but also for commercial applications. For this reason, this thesis has focused on SiGe BiCMOS based X-Band T/R Module, specifically on its two significant blocks; Low Noise Amplifier (LNA), and Phase Shifter. Low Noise Amplifier is the first block of the receiver chain of the T/R Module; as a result its performance is very influential on the metrics of receiver, such as Noise Figure (NF), and gain. In this thesis, designing procedures for three different high dynamic range LNA structures are described, using 0.13μm SiGe IHP-Microelectronics and 0.13μm SiGe IBM technology. To achieve a high dynamic range, three different methodologies implemented and compared; single-stage cascode LNA, telescopic LNA, and two-stage cascode LNA. Among these, two-stage cascode LNA achieved better performance metrics of -3.72dBm level for input-compression point, total gain exceeding 20.5dB, a NF performance of about 2dB, and a power consumption of 115.8mW. Phase Shifter is used both in receiver and transmitting chain, as a result it is also crucial for the performance of the T/R Module. The design, implemented in 0.13μm SiGe IBM technology, had aimed to combine advantages of different topologies, such as passive phase shifter and vector modulator, to achieve a high phase resolution in wide bandwidth, and high linearity. The designed hybrid Phase Shifter achieves 6-Bit operation with 6.75GHz of bandwidth and 15dBm of input-P1dB. Moreover, design can be switched to 7-Bit phase shifter with 4.5GHz, without requiring any additional circuitry

4-bit SiGe phase shifter using distributed active switches and variable gain amplifier for x-band phased array applications

This paper presents a 4-bit digitally controlled phase shifter for X-band (8-12.5 GHz) phased-arrays, implemented in 0.25-mu m SiGe BiCMOS process. Distributed active switches are utilized in first three bits. On-chip inductances are used to provide 22.5 degrees phase shift steps. The placement and the geometry of these inductances are optimized for minimum phase error and insertion loss. In order to compensate the gain variations of this stage, a single stage variable gain amplifier is used. The fourth bit which provides 0/180 degrees phase shift is obtained in third amplification stage, with switching between common base - common emitter configuration. With utilization of this technique overall phase error is significantly decreased and overall gain is increased. The phase shifter achieves 7dB gain with 3 dB of gain error. 360 degrees phase shift is achieved in 4 bit resolution with a phase error of 0.5 degrees at center frequency of 10GHz, and maximum 22 degrees phase error in 4.5 GHz bandwidth. The chip size is 2150 mu m x 1040 mu m including the bondpads. These performance parameters are comparable with the state of the art using similar technology

Active positive sloped equalizer for x-band SiGe BiCMOS phased array applications

This work presents an active equalizer circuit with positive gain slope at X-Band (8 - 12 GHz). Compared to passive examples, the active equalizer realized better filter and impedance characteristics in frequency of interest with increased functionality for a single amplification stage. It achieved close to 10 dB of peak gain, a + 1.13 dB/GHz gain slope with 2.8 dB NF by utilizing cascode topology. The design reaches a -1.5 dBm input-referred compression point (input-P1dB) while consuming 46 mW of power. To the best of authors’ knowledge, the presented work achieves the best on-chip gain, a gain slope and NF performance in the literature as an equalizer that utilizes SiGe BiCMOS technology

Figure 1: Simple block diagram of a SiGe BiCMOS On chip T/R module 4-Bit SiGe Phase Shifter using Distributed Active Switches and Variable Gain Amplifier For X-Band Phased Array Applications

Abstract-This paper presents a 4-bit digitally controlled phase shifter for X-band (8-12.5 GHz) phased-arrays, implemented in 0.25-µm SiGe BiCMOS process. Distributed active switches are utilized in first three bits. On-chip inductances are used to provide 22.5° phase shift steps. The placement and the geometry of these inductances are optimized for minimum phase error and insertion loss. In order to compensate the gain variations of this stage, a single stage variable gain amplifier is used. The fourth bit which provides 0/180° phase shift is obtained in third amplification stage, with switching between common basecommon emitter configuration. With utilization of this technique overall phase error is significantly decreased and overall gain is increased. The phase shifter achieves 7dB gain with 3 dB of gain error. 360° phase shift is achieved in 4 bit resolution with a phase error of 0.5° at center frequency of 10GHz, and maximum 22° phase error in 4.5 GHz bandwidth. The chip size is 2150 µm x 1040 µm including the bondpads. These performance parameters are comparable with the state of the art using similar technology

An x-band 6-bit active phase shifter

This paper presents a 6-bit active phase shifter using a new vector-sum method for X-band (8-12 GHz) phased arrays in 0.13 mu m SiGe BiCMOS process. An RC filter is used to generate two orthogonal vectors which are then fed into four VGAs, two using the common-base and two using the common-emitter topology. This generates 4 vectors of 0 degrees, 90 degrees, 180 degrees and 270 degrees which are scaled and added by varying the gains of the VGAs to generate any phase between 0-360 degrees. The gains of the VGAs are adjusted with analog voltage control using the current-steering method. The outputs of the VGAs are connected together with a common load in order to add the vectors in current-domain. The phase shifter achieves < 5.6 degrees RMS phase error over 8-12 GHz and < 3.1 degrees RMS phase error over 9-11 GHz. The phase shifter has a power consumption of 16.6 mW from a 2V supply. The chip size is 850 mu m x 532 mu m including the probing pads. These performance parameters are comparable with the state of the art of the technology in literature

A wideband low noise SiGe medium power amplifier for x-band phased array applications

This paper presents a Medium Power Amplifier (MPA) for X-Band Phased Array RADAR applications in 0.25 mu m SiGe technology. The MPA is designed such that it achieves high output power and low noise simultaneously that enables its use in Transmitter/ Receiver (T/R) core module as a Low Noise Amplifier (LNA). The MPA achieves 23.6dB peak gain and 17.3dB maximum output power at 10GHz with a power consumption of 190mW. Its input and output is matched in a 7 GHz of bandwidth, while its mean Noise Figure (NF) is about 3dB throughout the defined bandwidth. According to authors' knowledge, this work presents state-of-the-art wideband MPA performances in literature, with 7GHz of operational bandwidth and 17.3dBm output power

A SiGe BiCMOS bypass low-noise amplifier for x-band phased array RADARs

This paper presents a bypass low noise amplifier (LNA) for X-band phased array applications in 0.25μm SiGe BiCMOS technology. The trade-off between gain and bypass modes is considered to achieve high gain as well as low noise figure for gain mode while maintaining reasonable insertion loss with high power handling capability in bypass mode. In gain mode, the LNA achieves a measured gain of 17-14.2 dB and a noise figure of 1.75-1.95 dB over the 8-12 GHz band while consuming 27.4mW of DC-power. The measured input-referred I-dB compression point (IP 1dB ) is -3.9 dBm at 10 GHz. When operating in bypass mode, the measured insertion loss is 6.5-5.95 dB over the entire X-band with the measured IP 1dB of 15.1 dBm at 10 GHz, and it dissipates only 1μW power. Thanks to the bypassing technique, an increase of about 19 dB is achieved for IP 1dB in bypass mode compare to the gain mode. The measured return losses are better than 10 dB for both operating modes over whole X-band. The effective chip area excluding the pads is 0.3 mm 2